Senior ASIC Timing Engineer

Job Summary

A company is looking for a Senior ASIC Timing Engineer to join their advanced technology team.

Key Responsibilities

• Manage all aspects of timing including analysis, closure, and methodology for next generation designs
• Optimize design tradeoffs between frequency, power, area, congestion, and yield
• Oversee DFT/Test timing aspects such as constraints, analysis, convergence, and ECO implementation

Required Qualifications

• BS in Electrical or Computer Engineering or equivalent experience
• 8+ years of experience in Physical design/Timing
• Experience in full-chip/sub-chip Static Timing Analysis (STA) and timing constraints management
• In-depth understanding of multiplexed scan logic and constraints
• Hands-on knowledge of industry standard Timing/STA EDA tools