Verification Engineer

Job Summary

A company is looking for a Verification Engineer.

Key Responsibilities

• Develop, implement, and execute verification plans for digital blocks within PMICs
• Create and maintain test benches, verification environments, and regression tests
• Collaborate with analog/mixed-signal teams to verify digital-analog interactions

Required Qualifications

• BS or MS in Electrical Engineering, Computer Engineering, or a related field
• Minimum 6-8 years of experience in the field
• Solid understanding of digital logic design and power management concepts
• Experience with Verilog/SystemVerilog and Cadence simulation tools
• Scripting skills in Python, Tcl, Perl, or Shell for automation