Job Summary
A company is looking for a Digital Design Engineer to contribute to edge and FPGA development.
Key Responsibilities
- Design and implement digital logic using VHDL and Verilog
- Perform RTL simulation and debugging using industry-standard tools
- Write Python scripts for test automation and simulation workflows
Required Qualifications
- 3+ years of experience with VHDL and Verilog
- 3+ years of experience with Python
- 5+ years of experience with RTL simulation and debugging
- Comfortable working in Linux and command-line environments
- Knowledge of fixed point math and its implementation in hardware
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