Senior ASIC Synthesis Engineer

Job Summary

A company is looking for a Senior ASIC Synthesis Engineer to join their advanced technology team.

Key Responsibilities

• Own RTL synthesis and gate level optimization tasks
• Collaborate with physical design to address timing, area, and congestion tradeoffs
• Drive timing closure and power/area optimization across multiple design blocks

Required Qualifications

• BS or MS in Electrical Engineering, Computer Engineering, or equivalent experience
• 8+ years of experience in front-end ASIC synthesis and integration
• Deep understanding of Verilog RTL design and digital design principles
• Proven experience with industry-standard EDA tools for synthesis
• Hands-on experience with timing analysis, constraint management, and post-synthesis ECO flows