Senior ASIC Clock Engineer

Job Summary

A company is looking for a Senior ASIC Clock Engineer to work on next-generation networking chips.

Key Responsibilities

• Micro architect and design next-generation clock topologies and modules
• Collaborate with multiple teams to improve Power, Performance, and Area (PPA) of ASIC designs
• Support end-to-end ASIC execution, including design implementation and post-silicon activities

Required Qualifications

• BSc or MSc degrees in Electrical Engineering or equivalent experience
• At least 6+ years of experience in RTL design and circuit optimization
• Deep understanding of logic optimization techniques and PPA trade-offs
• Prior experience with clock IPs such as PLL and DLL is preferred
• Knowledge of sub-micron silicon issues like noise and cross-talk is a bonus