Job Summary
A company is looking for a Senior VLSI Physical Verification Methodology Engineer.
Key Responsibilities
- Develop physical verification methodologies for graphics processors and SOCs
- Participate in creating physical verification flows for new technologies, enhancing automation and workflows
- Collaborate with design teams to improve DRC feedback and correlation
Required Qualifications
- BS/MS in Electrical Engineering or related field (or equivalent experience)
- Minimum 4+ years of physical implementation experience with at least 2+ years in physical verification
- Familiarity with chip design aspects including Floor planning, Clock and Power distribution, Place and Route
- Strong knowledge of Physical Verification debug and experience with DRC/LVS/Antenna issues
- Proficient in writing DRC/LVS rules and scripting in Python/Perl or related automation languages
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